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LeoNatan
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Location: Ramat Gan, Israel 🇮🇱
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 Posted: Wed, 30th Jul 2014 03:24 Post subject: Intel’s Cannonlake |
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A "bit" early, but here we go.
http://wccftech.com/intels-cannonlake-10nm-microarchitecture-due-2016-compatible-union-bay-union-point-pch/
| Quote: | Intel’s Cannonlake 10nm Microarchitecture is Due For 2016 – Compatible On Union Bay With Union Point PCH
The first details of Intel’s next generation 10nm Cannonlake microarchitecture which arrives in 2016 have been revealed. The Cannonlake microarchitecture being a die shrink is regarded as a “TOCK” as interpreted through the Intel Tick-Tock model, hence it will replace the Skylake platform utilizing the benefits of the same processor architecture on a smaller 10nm node.
If thing’s go smooth with Skylake, then Cannonlake will hit shelves in 2016 available for both desktop and mobile platforms. Currently, the Intel Broadwell has disrupted due to 14nm manufacturing issues faced by Intel fab unit and won’t arrive market till late 2014. The only Broadwell processors consumers will get these year will be aimed at mobile form factors while the desktop processors will arrive in early 2015. Moving in 2015, Intel will have not one but two different desktop platforms, the Broadwell “Crescent Bay” platform which will make use of the Wild Cat point 9-Series chipset and the Skylake “Sky Bay” platform which will make use of the Sunrise point chipset.
Both platforms will seem to co-exist and platform details for Skylake have already been leaked out. The Intel Skylake platform will make use of a new x86 core architecture leveraging the IPC performance on a 14nm die node. Compared to Broadwell, which makes use of the Haswell architecture and a 14nm die shrink, the new architecture will deliver improved graphics in the form of GT4e and several chip enhancements such as cease usage of FVIR.
The successor to Skylake has been codenamed Cannonlake (previously known as Skymont), will feature a 10nm process die and the architecture of Skylake before it resulting in a more power efficient design. The Cannonlake platform will be known as Union Bay and would include the Union Point 200-Series chipset which will replace the Sunrise Point 100-Series chipset (Z170 on desktop platform). The same platform will be available on notebook and Ultrabook platforms. Little is known regarding Cannonlake at the moment and we might not even get to see it in action until IDF 2015 while launch is planned sometime in 2016. |
Will most likely use the same LGA 1151 socket as Skylake.
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| Posted: Wed, 30th Jul 2014 13:27 Post subject: |
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Them nanometers
Looking forward to my next upgrade in 2017.
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| Posted: Wed, 30th Jul 2014 16:24 Post subject: |
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10nm = 100 silicon atoms. At that size quantum tunneling starts becoming a problem. I wonder if they're doing anything to solve it or is it not significant enough yet.
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LeoNatan
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Location: Ramat Gan, Israel 🇮🇱
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| Posted: Wed, 30th Jul 2014 18:14 Post subject: |
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| BearishSun wrote: | | 10nm = 100 silicon atoms. At that size quantum tunneling starts becoming a problem. I wonder if they're doing anything to solve it or is it not significant enough yet. |
Intel is working in 7nm and 5nm chips as well. |
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Morphineus
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| Posted: Wed, 30th Jul 2014 18:28 Post subject: |
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Should be under 3nm that Quantum tunneling becomes a problem. So they should be fine for a while.
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| Posted: Wed, 30th Jul 2014 18:46 Post subject: |
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I'm wondering how they are doing it though. With 10nm the gate length is 5-6nm which they have already says can show significant effects of quantum tunneling.
Anyway found it: http://www.extremetech.com/computing/162376-7nm-5nm-3nm-the-new-materials-and-transistors-that-will-take-us-to-the-limits-of-moores-law
They're not using silicon for the transistor fins, but instead silicon germanium which I'm guessing has less gaps and better handles tunneling. (I'm guessing, I don't think Intel made a statement on it)
Supposedly it also has lower power consumption and is in general a higher quality material so we might see better overclocking potential?
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| Posted: Wed, 30th Jul 2014 18:51 Post subject: |
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| MORPHINEUS wrote: | | Should be under 3nm that Quantum tunneling becomes a problem. So they should be fine for a while. |
The transistor is 10nm but the gate is only 5nm (distance that needs to be tunneled through), which is a problem I believe. Electrons in silicon have shown to tunnel 15nm, although the average is only around 1.2nm. That seems like it would be significant probability for it to happen at 5nm.
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Morphineus
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| Posted: Wed, 30th Jul 2014 18:55 Post subject: |
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| BearishSun wrote: | | MORPHINEUS wrote: | | Should be under 3nm that Quantum tunneling becomes a problem. So they should be fine for a while. |
The transistor is 10nm but the gate is only 5nm (distance that needs to be tunneled through), which is a problem I believe. Electrons in silicon have shown to tunnel 15nm, although the average is only around 1.2nm. That seems like it would be significant probability for it to happen at 5nm. |
Ah thanks, did not know that.  |
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| Posted: Sun, 3rd Aug 2014 23:49 Post subject: |
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can anybody explain quantum tunneling ?
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| Posted: Mon, 4th Aug 2014 00:29 Post subject: |
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At very basic level: if things are small enough then particles can go through the barriers. Imagine you have 2 electric wires small enough and very close to each other and only 1 of them has current running through. Then because of quantum tunneling some % of particles(electrons) may tunnel through the wall between them and now the second wire will have some electrons running through it, basically it messes up all signals.
This is a good gif to illustrate it:
http://commons.wikimedia.org/wiki/File:EffetTunnel.gif#mediaviewer/File:EffetTunnel.gif
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| Posted: Mon, 4th Aug 2014 09:01 Post subject: |
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Tunneling effects will almost certainly be a lot smaller than classical effects in that example. The electric current in the first wire induces a magnetic field which agian induces an electric current in the other wire. A classical effect discovered by Ørsted back around 1800.
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Epsilon
Dr. Strangelove
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| Posted: Mon, 4th Aug 2014 16:15 Post subject: |
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Theres so much cool intel tech coming in the next year. And I was all set on buying a DDR4 setup this christmas. Now I'm not so sure.
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LeoNatan
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Location: Ramat Gan, Israel 🇮🇱
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| Posted: Mon, 4th Aug 2014 17:01 Post subject: |
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| Epsilon wrote: | | Theres so much cool intel tech coming in the next year. And I was all set on buying a DDR4 setup this christmas. Now I'm not so sure. |
I think you should wait at least for Skylake. It will introduce the new 1151 socket and will have DD4 support. |
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Epsilon
Dr. Strangelove
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| Posted: Sat, 9th Aug 2014 19:44 Post subject: |
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| DV2 wrote: | | LeoNatan wrote: | | Epsilon wrote: | | Theres so much cool intel tech coming in the next year. And I was all set on buying a DDR4 setup this christmas. Now I'm not so sure. |
I think you should wait at least for Skylake. It will introduce the new 1151 socket and will have DD4 support. |
It's like "Ooooh What he saaaaaaaaa-aa-aaaiiid" but in a positive way...I'm waiting for Skylake too  |
Yeah I looked into some benchmarks of the various cpu's and it's somewhat frightening that my 2600k is still able to keep up. It's even oc'd, been @4.5ghz rock solid since I put it in and it's what? 3 years or so now. Not that I mind of course, but progress does seem to have slowed down a bit hardware wise. |
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LeoNatan
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Location: Ramat Gan, Israel 🇮🇱
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| Posted: Mon, 23rd Feb 2015 20:28 Post subject: |
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| Posted: Mon, 23rd Feb 2015 21:03 Post subject: |
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is there a noticeable performance boost at DDR4?
| Lutzifer wrote: | | and yes, mine is only average |
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LeoNatan
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Location: Ramat Gan, Israel 🇮🇱
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| Posted: Fri, 6th Jan 2017 11:04 Post subject: |
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JBeckman
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couleur
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| Posted: Fri, 10th Feb 2017 09:50 Post subject: |
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So 15% clock increase, huh?
"Enlightenment is man's emergence from his self-imposed nonage. Nonage is the inability to use one's own understanding without another's guidance. This nonage is self-imposed if its cause lies not in lack of understanding but in indecision and lack of courage to use one's own mind without another's guidance. Dare to know! (Sapere aude.) "Have the courage to use your own understanding," is therefore the motto of the enlightenment."
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LeoNatan
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Posts: 73196
Location: Ramat Gan, Israel 🇮🇱
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| Posted: Fri, 10th Feb 2017 09:53 Post subject: |
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| couleur wrote: | | So 15% clock increase, huh? |
Not necessarily. Could be IPC (instructions per cycle) improvements. |
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couleur
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| Posted: Fri, 10th Feb 2017 10:56 Post subject: |
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It would be a real step forward.
"Enlightenment is man's emergence from his self-imposed nonage. Nonage is the inability to use one's own understanding without another's guidance. This nonage is self-imposed if its cause lies not in lack of understanding but in indecision and lack of courage to use one's own mind without another's guidance. Dare to know! (Sapere aude.) "Have the courage to use your own understanding," is therefore the motto of the enlightenment."
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| Posted: Fri, 10th Feb 2017 11:54 Post subject: |
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nobody said thats cannonlake, i would more likely assume its kaby lake refresh
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LeoNatan
☢ NFOHump Despot ☢
Posts: 73196
Location: Ramat Gan, Israel 🇮🇱
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| Posted: Fri, 10th Feb 2017 23:29 Post subject: |
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| couleur wrote: | | It would be a real step forward. |
I think every generation so far from Intel has been 10-15% improved IPC; this is how they achieve battery life optimizations - they lower clock and rely on the improved IPC to provide similar or better performance despite the reduced clock speed. |
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