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LeoNatan
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Posts: 73219
Location: Ramat HaSharon, Israel 🇮🇱
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 Posted: Tue, 21st Mar 2017 23:23 Post subject: AMD cannot write CPUs |
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https://www.techpowerup.com/231536/amd-ryzen-machine-crashes-to-a-sequence-of-fma3-instructions
| Quote: | AMD Ryzen Machine Crashes to a Sequence of FMA3 Instructions
An AMD Ryzen 7-1800X powered machine was found to be crashing upon execution of a very specific set of FMA3 instructions by Flops version 2, a simple open-source CPU benchmark by Alexander "Mystical" Yee. An important point to note here is that this little known benchmark has been tailored by its developer to be highly specific to the CPU micro-architecture, with separate binaries for each major x64 architecture (eg: Bulldozer, Sandy Bridge, Haswell, Skylake, etc.), and as such the GitHub repository does not have a "Zen" specific binary.
Members of the HWBot forums found that Ryzen powered machines crash on running the Haswell-specific binary, at "Single-Precision - 128-bit FMA3 - Fused Multiply Add." The Haswell-specific binary (along with, we imagine, Skylake), adds support for the FMA3 instruction-set, which Ryzen supports, and which lends some importance to the discovery of this bug. What also makes this important is because a simple application, running at user privileges (i.e. lacking special super-user/admin privileges), has the ability to crash the machine. Such a code could even be executed through virtual machines, and poses a security issue, with implications for AMD's upcoming "Naples" enterprise processor launch. |
You had one fucking job! 
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LeoNatan
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Posts: 73219
Location: Ramat HaSharon, Israel 🇮🇱
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| Posted: Tue, 21st Mar 2017 23:25 Post subject: |
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And the comments are hilarious.  Bunch of crybaby AMD fankiddies, unable to comprehend what a standard instruction set is.
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| Posted: Tue, 21st Mar 2017 23:52 Post subject: |
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though amd stated yesterday they fixed it with a bios update. dunno if thats good or not. fixing an hardware error with an update? what have they done? just deactivated a few instructions? which may lead to other problems?
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LeoNatan
☢ NFOHump Despot ☢
Posts: 73219
Location: Ramat HaSharon, Israel 🇮🇱
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| Posted: Wed, 22nd Mar 2017 00:01 Post subject: |
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Usually CPUs are "patched" with microcode updates. But are you sure they have fixed this issue specifically?
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| Posted: Wed, 22nd Mar 2017 00:03 Post subject: |
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Last edited by Interinactive on Mon, 4th Oct 2021 09:59; edited 1 time in total
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LeoNatan
☢ NFOHump Despot ☢
Posts: 73219
Location: Ramat HaSharon, Israel 🇮🇱
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| Posted: Wed, 22nd Mar 2017 07:56 Post subject: I have left. |
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Werelds
Special Little Man
Posts: 15098
Location: 0100111001001100
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| Posted: Wed, 22nd Mar 2017 10:21 Post subject: |
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Guessing you're not aware of the Skylake bug then Leo?
Let Prime95 get to 14942209 with FFT and Skylake would kill itself too before the microcode update 
You laugh about the "crybaby AMD fankiddies", I laugh about all the hypocritical retards acting as if this is something new. Every single Intel (and AMD) architecture has had bugs. It has nothing to do with "standard" instruction sets, they support the instruction set just fine. But the physical switching is shorting out somewhere when it shouldn't; what the microcode updates do is usually to reroute these instructions. Sometimes at a small performance cost, sometimes not. Very rarely do they actually need to disable these instructions.
But it's easy to forget about this Skylake bug because it's Intel I guess. Or their ongoing issues with AVX at least up to and including Skylake; not sure about Kaby. Or Broadwell/Haswell's TSX that Intel had to disable altogether. Or Broadwell's P-state issues. There's a reason we have things like this and people have made things like this. And it's not new, just Google "Intel FDIV"
CPUs have bugs. They always have, they always will. In fact, we'll see more going forward, as it becomes harder and harder to avoid them at the crazy small scales Intel and AMD have to design their architectures at now. A lot of these bugs are actually physical flaws in the designs, because something leaks in an unexpected place for a specific instruction; they then change that instruction to use different ALUs/registers to work around that.
The only reason this is such a "thing" right now is because it's AMD's first noteworthy CPU product in a very long time. Not because it's uncommon.
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